Dynamic reconfiguration of modular multi-processor systems in SoPC devices

Currently, the density of transistors that electronic devices now allow is such that the integration of complete digital systems in a single integrated circuit is now possible. With the aim of reducing the period of design and development and enabling the tackling of these kinds of designs possible, these are made up of a base of modules or cores. Given their complexity, these modules often include one or more processors, whereby, in these cases, multi-processor systems are possible.

This level of integration has also been extended to reconfigurable FPGA devices, this alternative being one of the most utilised given the flexibility that it offers. However, the most common use of its capacity for reconfiguration is limited in order to facilitate the prototype phase of the design and, in other cases, to carry out subsequent updates thereof.

Nevertheless, the most recent FPGAs allow part of their configuration to be modified while the rest of the configured circuit continues to operate. This ability, known as dynamic partial reconfiguration, is of particular interest in the design of digital systems involving modules in a single integrated circuit. In these cases, the procedure carried out on the chip can also determine changes of context for the circuits or programmes of the modules and then apply them.

The specific term used to describe this type of design is self-reconfigurable systems.

The auto-reconfiguration operation is complex. In order to carry it out with some degree of guarantee in a multi-processor system based on cores, apart from the fact that the FPGA admits dynamic partial reconfiguration at a technological level, a system of control for the design system itself is needed.

This PhD thesis proposes a self-reconfiguration control system for multi-processor systems based on cores. Initially, a generalised plan for the control system is carried out, valid for incorporation into designs that use standard specifications for the most common systems design on a chip. This generalisation takes the form of a reconfigurable multi-processor model, defining on this basis the characteristics of the elements required in the control infrastructure. In order to facilitate the analysis of the suitability of the self-reconfiguration in a determined design, a modelling of the resources needed for the infrastructure is carried out and the times involved determined.

The theoretical system outlined is validated using concrete reconfigurable technology. To this end, all the elements specified in the control infrastructure of the reconfiguration are implemented and additional tools enabling multi-processor and multi-context designs are developed. This infrastructure is applied to three platforms expressly designed to test the self-reconfiguration with the proposed control system. These trials required the construction of a special prototype that enabled total control of the FPGA configuration processes.